SystDigit-Projet.git - Projet de Système Digital

	Commit message (Collapse)	Author	Age	Files	Lines
*	Added FEED/FED signals in protocol.	Alex AUVOLAT	2014-01-09	1	-0/+9
\|
*	Monitor now works correctly.	Alex AUVOLAT	2014-01-03	1	-0/+4
\|
*	Added simulator monitor tool.	Alex AUVOLAT	2014-01-03	1	-0/+11
\|
*	Started CPU implementation.	Alex AUVOLAT	2014-01-02	1	-2/+2
\|
*	Tabs to spaces ; deleted Caml simulator (useless anyways)	Alex AUVOLAT	2013-12-17	1	-191/+191
\|
*	RAM gives result immediately..	Alex AUVOLAT	2013-11-19	1	-9/+4
\|
*	Minor changes.	Alex AUVOLAT	2013-11-12	1	-1/+1
\|
*	Added ROM support, coded a 24/60/60 watch with output for 7-bit LCD display	Alex AUVOLAT	2013-11-11	1	-32/+6
\|
*	Minor style changes.	Alex AUVOLAT	2013-11-09	1	-2/+3
\|
*	Simulator fixed.	Alex AUVOLAT	2013-11-08	1	-3/+3
\|
*	[WIP] Change dumb netlist format in scheduler and simulator.	Alex AUVOLAT	2013-11-08	1	-67/+95
\|
*	Added netlist simplification passes (not yet quite complete !)	Alex AUVOLAT	2013-11-05	1	-5/+11
\|
*	C simulator quite completed.	Alex AUVOLAT	2013-11-04	1	-0/+190
\|
*	Added stub C simulator (defined dumb-down syntax for netlists).	Alex AUVOLAT	2013-11-04	1	-0/+23