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| author | Alex AUVOLAT <alex.auvolat@ens.fr> | 2014-01-02 22:30:11 +0100 |
|---|---|---|
| committer | Alex AUVOLAT <alex.auvolat@ens.fr> | 2014-01-02 22:30:11 +0100 |
| commit | 85bc61cb7fa8f4b9af78064cb65fbad49a109d5f (patch) | |
| tree | 5116b1c423864f3cde8f1002b7a4dabb62e88fff /csim/sim.c | |
| parent | 4e1aaf316457f4d4f045fd3ebe500cd70f6bafcc (diff) | |
| download | SystDigit-Projet-85bc61cb7fa8f4b9af78064cb65fbad49a109d5f.tar.gz SystDigit-Projet-85bc61cb7fa8f4b9af78064cb65fbad49a109d5f.zip | |
Started CPU implementation.
Diffstat (limited to 'csim/sim.c')
| -rw-r--r-- | csim/sim.c | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -121,8 +121,8 @@ void machine_step(t_machine *m) { } break; case C_ROM: - if (p->eqs[i].Rom.rom != NULL) { - a = m->var_values[p->eqs[i].Rom.read_addr]; + a = m->var_values[p->eqs[i].Rom.read_addr]; + if (p->eqs[i].Rom.rom != NULL && a < p->eqs[i].Rom.rom->words_defined) { v = p->eqs[i].Rom.rom->data[a]; } else { v = 0; |