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| author | Alex AUVOLAT <alex.auvolat@ens.fr> | 2013-11-19 17:13:52 +0100 |
|---|---|---|
| committer | Alex AUVOLAT <alex.auvolat@ens.fr> | 2013-11-19 17:13:52 +0100 |
| commit | f91d7484c8d5af62dff97eb9ce5a5ac85aba2005 (patch) | |
| tree | 98d98eacf343fe14eb449ac83fb89790707fd15a /csim/sim.c | |
| parent | 96d05da16df5b6b32a0776ef11d6ad241e7af9bb (diff) | |
| download | SystDigit-Projet-f91d7484c8d5af62dff97eb9ce5a5ac85aba2005.tar.gz SystDigit-Projet-f91d7484c8d5af62dff97eb9ce5a5ac85aba2005.zip | |
RAM gives result immediately..
Diffstat (limited to 'csim/sim.c')
| -rw-r--r-- | csim/sim.c | 13 |
1 files changed, 4 insertions, 9 deletions
@@ -90,15 +90,6 @@ void machine_step(t_machine *m) { p->vars[p->regs[i].dest].name, m->reg_data[i]); } - for (i = 0; i < p->n_rams; i++) { - e = m->var_values[p->rams[i].write_enable]; - if (e == 0) { - a = m->var_values[p->rams[i].read_addr]; - b = m->ram_data[i][a]; - m->var_values[p->rams[i].dest] = b; - if (DEBUG) fprintf(stderr, "Read ram %lx = %lx\n", a, b); - } - } // DO THE LOGIC for (i = 0; i < p->n_eqs; i++) { @@ -167,6 +158,10 @@ void machine_step(t_machine *m) { if (DEBUG) fprintf(stderr, "select %d %lx->%lx .. ", p->eqs[i].Select.i, a, v); break; + case C_READRAM: + a = m->var_values[p->eqs[i].ReadRAM.source]; + v = m->ram_data[p->eqs[i].ReadRAM.ram_id][a]; + if (DEBUG) fprintf(stderr, "Read ram %lx = %lx\n", a, v); } m->var_values[p->eqs[i].dest_var] = v & (p->vars[p->eqs[i].dest_var].mask); if (DEBUG) fprintf(stderr, "%s &%lx : %lx\n", |