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authorAlex AUVOLAT <alex.auvolat@ens.fr>2013-11-19 17:13:52 +0100
committerAlex AUVOLAT <alex.auvolat@ens.fr>2013-11-19 17:13:52 +0100
commitf91d7484c8d5af62dff97eb9ce5a5ac85aba2005 (patch)
tree98d98eacf343fe14eb449ac83fb89790707fd15a /csim
parent96d05da16df5b6b32a0776ef11d6ad241e7af9bb (diff)
downloadSystDigit-Projet-f91d7484c8d5af62dff97eb9ce5a5ac85aba2005.tar.gz
SystDigit-Projet-f91d7484c8d5af62dff97eb9ce5a5ac85aba2005.zip
RAM gives result immediately..
Diffstat (limited to 'csim')
-rw-r--r--csim/load.c10
-rw-r--r--csim/sim.c13
-rw-r--r--csim/sim.h10
-rw-r--r--csim/util.c2
4 files changed, 19 insertions, 16 deletions
diff --git a/csim/load.c b/csim/load.c
index e6fcf29..607e0e2 100644
--- a/csim/load.c
+++ b/csim/load.c
@@ -84,11 +84,10 @@ t_program *load_dumb_netlist (FILE *stream) {
fscanf(stream, "%d", &(p->n_rams));
p->rams = malloc(p->n_rams * sizeof(t_ram));
for (i = 0; i < p->n_rams; i++) {
- fscanf(stream, "%d %d %d %d %d %d %d\n",
- &(p->rams[i].dest),
+ fscanf(stream, "%d %d %d %d %d\n",
&(p->rams[i].addr_size),
&(p->rams[i].word_size),
- &(p->rams[i].read_addr), &(p->rams[i].write_enable),
+ &(p->rams[i].write_enable),
&(p->rams[i].write_addr), &(p->rams[i].data));
}
@@ -156,6 +155,11 @@ t_program *load_dumb_netlist (FILE *stream) {
&(p->eqs[i].Select.i),
&(p->eqs[i].Select.source));
break;
+ case C_READRAM:
+ fscanf(stream, "%d %d ",
+ &(p->eqs[i].ReadRAM.ram_id),
+ &(p->eqs[i].ReadRAM.source));
+ break;
}
}
diff --git a/csim/sim.c b/csim/sim.c
index db2c736..db30ea3 100644
--- a/csim/sim.c
+++ b/csim/sim.c
@@ -90,15 +90,6 @@ void machine_step(t_machine *m) {
p->vars[p->regs[i].dest].name,
m->reg_data[i]);
}
- for (i = 0; i < p->n_rams; i++) {
- e = m->var_values[p->rams[i].write_enable];
- if (e == 0) {
- a = m->var_values[p->rams[i].read_addr];
- b = m->ram_data[i][a];
- m->var_values[p->rams[i].dest] = b;
- if (DEBUG) fprintf(stderr, "Read ram %lx = %lx\n", a, b);
- }
- }
// DO THE LOGIC
for (i = 0; i < p->n_eqs; i++) {
@@ -167,6 +158,10 @@ void machine_step(t_machine *m) {
if (DEBUG) fprintf(stderr, "select %d %lx->%lx .. ",
p->eqs[i].Select.i, a, v);
break;
+ case C_READRAM:
+ a = m->var_values[p->eqs[i].ReadRAM.source];
+ v = m->ram_data[p->eqs[i].ReadRAM.ram_id][a];
+ if (DEBUG) fprintf(stderr, "Read ram %lx = %lx\n", a, v);
}
m->var_values[p->eqs[i].dest_var] = v & (p->vars[p->eqs[i].dest_var].mask);
if (DEBUG) fprintf(stderr, "%s &%lx : %lx\n",
diff --git a/csim/sim.h b/csim/sim.h
index d77465a..80fab56 100644
--- a/csim/sim.h
+++ b/csim/sim.h
@@ -12,6 +12,7 @@
#define C_CONCAT 5
#define C_SLICE 6
#define C_SELECT 7
+#define C_READRAM 8
// Binary operators
#define OP_OR 0
@@ -45,9 +46,8 @@ typedef struct {
} t_reg;
typedef struct {
- t_id dest;
int addr_size, word_size;
- t_id read_addr, write_enable, write_addr, data;
+ t_id write_enable, write_addr, data;
} t_ram;
typedef struct {
@@ -83,6 +83,10 @@ typedef struct {
int i;
t_id source;
} Select;
+ struct {
+ int ram_id;
+ t_id source;
+ } ReadRAM;
};
} t_equation;
@@ -127,6 +131,6 @@ void write_outputs(t_machine *m, FILE *stream);
// Implemented in util.c
int pow2(int exp);
t_value read_bool(FILE *stream, t_value *mask);
-int is_prefix(char *prefix, char *str);
+int is_prefix(const char *prefix, const char *str);
#endif
diff --git a/csim/util.c b/csim/util.c
index ef0ae32..c815e8e 100644
--- a/csim/util.c
+++ b/csim/util.c
@@ -35,7 +35,7 @@ t_value read_bool(FILE *stream, t_value *mask) {
return r;
}
-int is_prefix(char *prefix, char *str) {
+int is_prefix(const char *prefix, const char *str) {
while (*prefix) {
if (*prefix != *str) return 0;
prefix++;