SystDigit-Projet.git - Projet de Système Digital

	Commit message (Collapse)	Author	Age	Files	Lines
*	Implement lw/sw/lwr/swr ; optimize simplification pass order ; add comments ↵	Alex AUVOLAT	2014-01-03	1	-1/+15
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*	Started CPU implementation.	Alex AUVOLAT	2014-01-02	3	-7/+9
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*	Tabs to spaces ; deleted Caml simulator (useless anyways)	Alex AUVOLAT	2013-12-17	5	-507/+507
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*	RAM gives result immediately..	Alex AUVOLAT	2013-11-19	4	-16/+19
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*	Added a TODO, changed a few comments.	Alex AUVOLAT	2013-11-15	1	-1/+3
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*	Improvemenet of pow2 (suggested by T.Bourke)	Alex AUVOLAT	2013-11-12	1	-4/+1
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*	Minor changes.	Alex AUVOLAT	2013-11-12	1	-1/+1
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*	Added ROM support, coded a 24/60/60 watch with output for 7-bit LCD display	Alex AUVOLAT	2013-11-11	6	-42/+124
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*	Minor style changes.	Alex AUVOLAT	2013-11-09	2	-3/+5
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*	Simulator fixed.	Alex AUVOLAT	2013-11-08	1	-3/+3
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*	[WIP] Change dumb netlist format in scheduler and simulator.	Alex AUVOLAT	2013-11-08	3	-165/+172
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*	Documented the C simulator in the README file ; added a test file.	Alex AUVOLAT	2013-11-06	1	-1/+1
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*	Added netlist simplification passes (not yet quite complete !)	Alex AUVOLAT	2013-11-05	2	-8/+14
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*	Reorganized folders.	Alex AUVOLAT	2013-11-05	3	-3/+7
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*	C simulator quite completed.	Alex AUVOLAT	2013-11-04	4	-13/+242
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*	Added stub C simulator (defined dumb-down syntax for netlists).	Alex AUVOLAT	2013-11-04	5	-0/+345