SystDigit-Projet.git - Projet de Système Digital

	Commit message (Collapse)	Author	Age	Files	Lines
*	Document programs ; better time support in monitor.	Alex AUVOLAT	2014-01-04	1	-20/+69
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*	Started CPU implementation.	Alex AUVOLAT	2014-01-02	1	-4/+8
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*	Tabs to spaces ; deleted Caml simulator (useless anyways)	Alex AUVOLAT	2013-12-17	1	-72/+64
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*	RAM gives result immediately..	Alex AUVOLAT	2013-11-19	1	-3/+2
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*	Added a TODO, changed a few comments.	Alex AUVOLAT	2013-11-15	1	-0/+1
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*	Improvemenet of pow2 (suggested by T.Bourke)	Alex AUVOLAT	2013-11-12	1	-0/+17
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*	Updated README file.	Alex AUVOLAT	2013-11-12	1	-4/+5
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*	(nothing interesting)	Alex AUVOLAT	2013-11-12	1	-7/+21
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*	[WIP] Change dumb netlist format in scheduler and simulator.	Alex AUVOLAT	2013-11-08	1	-3/+45
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*	Documented the C simulator in the README file ; added a test file.	Alex AUVOLAT	2013-11-06	1	-17/+143
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*	More simplifcation passes...	Alex AUVOLAT	2013-11-05	1	-0/+9
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*	Added netlist simplification passes (not yet quite complete !)	Alex AUVOLAT	2013-11-05	1	-0/+16
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*	Added README file	Alex AUVOLAT	2013-11-04	1	-0/+38