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| author | Alex AUVOLAT <alex.auvolat@ens.fr> | 2013-11-19 17:13:52 +0100 |
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| committer | Alex AUVOLAT <alex.auvolat@ens.fr> | 2013-11-19 17:13:52 +0100 |
| commit | f91d7484c8d5af62dff97eb9ce5a5ac85aba2005 (patch) | |
| tree | 98d98eacf343fe14eb449ac83fb89790707fd15a /README | |
| parent | 96d05da16df5b6b32a0776ef11d6ad241e7af9bb (diff) | |
| download | SystDigit-Projet-f91d7484c8d5af62dff97eb9ce5a5ac85aba2005.tar.gz SystDigit-Projet-f91d7484c8d5af62dff97eb9ce5a5ac85aba2005.zip | |
RAM gives result immediately..
Diffstat (limited to 'README')
| -rw-r--r-- | README | 5 |
1 files changed, 2 insertions, 3 deletions
@@ -163,7 +163,7 @@ This is the description of the format currently used by the C simulator. <register destination variable> <register source variable> <ram list size> [for each ram] - <destination variable> <addr size> <word size> <read addr var> + <addr size> <word size> <write enable var> <write addr var> <data var> <equation list size> [for each equation] @@ -180,6 +180,7 @@ ID DESCR ARGS 5 Concat var_a var_b 6 Slice begin end var_id 7 Select number var_id +8 RAM Read ram_number var_id Operators : 0 OR @@ -248,8 +249,6 @@ TODO ---- - More advanced commands for the simulator (cf Jonathan's simulator) -- RAM reads give result immediately -- Optimisation : SELECT/SLICE a variable which is a CONCAT NEXT STEPS ---------- |