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-rw-r--r--camlsim/test/clock_div_sch.net9
1 files changed, 9 insertions, 0 deletions
diff --git a/camlsim/test/clock_div_sch.net b/camlsim/test/clock_div_sch.net
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+++ b/camlsim/test/clock_div_sch.net
@@ -0,0 +1,9 @@
+INPUT
+OUTPUT o
+VAR
+ _l_2, c, o
+IN
+_l_2 = REG o
+o = REG c
+c = NOT _l_2
+