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| author | Alex AUVOLAT <alex.auvolat@ens.fr> | 2013-10-31 18:15:01 +0100 |
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| committer | Alex AUVOLAT <alex.auvolat@ens.fr> | 2013-10-31 18:15:01 +0100 |
| commit | f253f98136def21b5e50c5922246e2ddfe315442 (patch) | |
| tree | 5ba21cf7a697bccaf58bf8072cb4c283be85a84e /camlsim/test/clock_div_sch.net | |
| parent | 0b269f32dd9b8d349f94793dad44e728473e9f0a (diff) | |
| download | SystDigit-Projet-f253f98136def21b5e50c5922246e2ddfe315442.tar.gz SystDigit-Projet-f253f98136def21b5e50c5922246e2ddfe315442.zip | |
Simulator started.
Diffstat (limited to 'camlsim/test/clock_div_sch.net')
| -rw-r--r-- | camlsim/test/clock_div_sch.net | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/camlsim/test/clock_div_sch.net b/camlsim/test/clock_div_sch.net new file mode 100644 index 0000000..0ae5cd9 --- /dev/null +++ b/camlsim/test/clock_div_sch.net @@ -0,0 +1,9 @@ +INPUT +OUTPUT o +VAR + _l_2, c, o +IN +_l_2 = REG o +o = REG c +c = NOT _l_2 + |