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authorAlex AUVOLAT <alex.auvolat@ens.fr>2013-11-19 17:13:52 +0100
committerAlex AUVOLAT <alex.auvolat@ens.fr>2013-11-19 17:13:52 +0100
commitf91d7484c8d5af62dff97eb9ce5a5ac85aba2005 (patch)
tree98d98eacf343fe14eb449ac83fb89790707fd15a /csim/load.c
parent96d05da16df5b6b32a0776ef11d6ad241e7af9bb (diff)
downloadSystDigit-Projet-f91d7484c8d5af62dff97eb9ce5a5ac85aba2005.tar.gz
SystDigit-Projet-f91d7484c8d5af62dff97eb9ce5a5ac85aba2005.zip
RAM gives result immediately..
Diffstat (limited to 'csim/load.c')
-rw-r--r--csim/load.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/csim/load.c b/csim/load.c
index e6fcf29..607e0e2 100644
--- a/csim/load.c
+++ b/csim/load.c
@@ -84,11 +84,10 @@ t_program *load_dumb_netlist (FILE *stream) {
fscanf(stream, "%d", &(p->n_rams));
p->rams = malloc(p->n_rams * sizeof(t_ram));
for (i = 0; i < p->n_rams; i++) {
- fscanf(stream, "%d %d %d %d %d %d %d\n",
- &(p->rams[i].dest),
+ fscanf(stream, "%d %d %d %d %d\n",
&(p->rams[i].addr_size),
&(p->rams[i].word_size),
- &(p->rams[i].read_addr), &(p->rams[i].write_enable),
+ &(p->rams[i].write_enable),
&(p->rams[i].write_addr), &(p->rams[i].data));
}
@@ -156,6 +155,11 @@ t_program *load_dumb_netlist (FILE *stream) {
&(p->eqs[i].Select.i),
&(p->eqs[i].Select.source));
break;
+ case C_READRAM:
+ fscanf(stream, "%d %d ",
+ &(p->eqs[i].ReadRAM.ram_id),
+ &(p->eqs[i].ReadRAM.source));
+ break;
}
}