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authorAlex Auvolat <alex.auvolat@ansys.com>2014-07-01 10:57:14 +0200
committerAlex Auvolat <alex.auvolat@ansys.com>2014-07-01 10:57:14 +0200
commit368a0b045d3df1aa126458cf485e07eab153924d (patch)
tree5ee7e0908d64fe4ac7398806b1324921acb4c38a /tests/source
parent88ecd2d5f2b27a09060313fd29fd087b92e6166e (diff)
downloadscade-analyzer-368a0b045d3df1aa126458cf485e07eab153924d.tar.gz
scade-analyzer-368a0b045d3df1aa126458cf485e07eab153924d.zip
Finish up EDDs
Diffstat (limited to 'tests/source')
-rw-r--r--tests/source/limitera.scade2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/source/limitera.scade b/tests/source/limitera.scade
index 2b87278..9bfb6d2 100644
--- a/tests/source/limitera.scade
+++ b/tests/source/limitera.scade
@@ -4,7 +4,7 @@ node limiter(x: int; d: int) returns (probe y: int)
var s, r: int;
let
assume in_bounded: x >= -bound and x <= bound;
- assume d_bounded: d = 16;
+ assume d_bounded: d >= 0 and d <= 16;
guarantee out_bounded: y >= -bound and y <= bound;
s = 0 -> pre y;
r = x - s;