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authorAlex Auvolat <alex.auvolat@ansys.com>2014-07-04 17:48:09 +0200
committerAlex Auvolat <alex.auvolat@ansys.com>2014-07-04 17:48:09 +0200
commit696d07415d52b092c9c69a9b1042a8bc9cd51a90 (patch)
tree00186f29dcd6e6467e18de8b4bfcd560ae43c620 /tests/source/test7.scade
parent108f38029404e8eb4b37c8892345917edfb3cac7 (diff)
downloadscade-analyzer-696d07415d52b092c9c69a9b1042a8bc9cd51a90.tar.gz
scade-analyzer-696d07415d52b092c9c69a9b1042a8bc9cd51a90.zip
Adapt non-EDD disjunction interpret to use two set of disjunction vars.
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