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authorAlex Auvolat <alex.auvolat@ansys.com>2014-06-26 18:03:33 +0200
committerAlex Auvolat <alex.auvolat@ansys.com>2014-06-26 18:03:33 +0200
commit11e7905ba16d4b13b5c2eda50a198391693e5d96 (patch)
treee083b92f611047eb5ae353aca497021a9611a108 /tests/source/limitera.scade
parentf3d89408ebb44f77f257b2cb51a4bdd74b9268d0 (diff)
downloadscade-analyzer-11e7905ba16d4b13b5c2eda50a198391693e5d96.tar.gz
scade-analyzer-11e7905ba16d4b13b5c2eda50a198391693e5d96.zip
Minor corrections.
- Use correect clock scope in typing - De-activate multi-valuated domain for enumerate vars + var couples. - Add comment explaining why it doesn't work
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