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authorAlex Auvolat <alex.auvolat@ansys.com>2014-06-27 16:59:29 +0200
committerAlex Auvolat <alex.auvolat@ansys.com>2014-06-27 16:59:29 +0200
commitea25c6e61f585b263d3eac44a463e37116ce1e7f (patch)
treec5bd80d45478871dcb245fe9e53e3a7a681cfb34 /main.ml
parent11e7905ba16d4b13b5c2eda50a198391693e5d96 (diff)
downloadscade-analyzer-ea25c6e61f585b263d3eac44a463e37116ce1e7f.tar.gz
scade-analyzer-ea25c6e61f585b263d3eac44a463e37116ce1e7f.zip
More work on EDDs.
Diffstat (limited to 'main.ml')
-rw-r--r--main.ml7
1 files changed, 3 insertions, 4 deletions
diff --git a/main.ml b/main.ml
index d526a76..dde682f 100644
--- a/main.ml
+++ b/main.ml
@@ -12,9 +12,7 @@ module ItvND = Nonrelational.ND(Intervals_domain.VD)
module AI_Itv = Abs_interp.I(Enum_domain.MultiValuation)(ItvND)
module AI_Rel = Abs_interp.I(Enum_domain.MultiValuation)(Apron_domain.ND)
-(*
module AI_Itv_EDD = Abs_interp_edd.I(ItvND)
-*)
(* command line options *)
let dump = ref false
@@ -82,6 +80,8 @@ let do_test_interpret prog verbose =
it 0 s0
let () =
+ AI_Itv_EDD.test ();
+
Arg.parse options (fun f -> ifile := f) usage;
if !ifile = "" then begin
@@ -117,9 +117,8 @@ let () =
if !ai_itv then AI_Itv.do_prog opt rp;
if !ai_rel then AI_Rel.do_prog opt rp;
- (*
+
if !ai_itv_edd then AI_Itv_EDD.do_prog opt rp;
- *)
end;
if !vtest then do_test_interpret prog true