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authorAlex Auvolat <alex.auvolat@ansys.com>2014-06-19 10:21:35 +0200
committerAlex Auvolat <alex.auvolat@ansys.com>2014-06-19 10:21:35 +0200
commita2da1268c4a9af6755723698b7b6ba669aa7fd46 (patch)
tree7deda3f5c6c33cc9935bc28bd4b879cf756ff59f /main.ml
parentced4b9677189ea837e267678e9774584b81b087f (diff)
downloadscade-analyzer-a2da1268c4a9af6755723698b7b6ba669aa7fd46.tar.gz
scade-analyzer-a2da1268c4a9af6755723698b7b6ba669aa7fd46.zip
Do some typing ; support multiple pre in abstract interpretation.
Diffstat (limited to 'main.ml')
-rw-r--r--main.ml6
1 files changed, 3 insertions, 3 deletions
diff --git a/main.ml b/main.ml
index e98dd5f..b63b35f 100644
--- a/main.ml
+++ b/main.ml
@@ -31,7 +31,7 @@ let options = [
]
let do_test_interpret prog verbose =
- let s0 = Interpret.init_state prog "test" in
+ let s0 = Interpret.init_state (Typing.root_prog prog "test") in
if verbose then begin
Format.printf "Init state:@.";
Interpret.print_state Format.std_formatter s0;
@@ -75,8 +75,8 @@ let () =
let prog = Rename.rename_prog prog in
if !dumprn then Ast_printer.print_prog Format.std_formatter prog;
- if !ai_itv then AI_Itv.do_prog !ai_widen_delay prog !ai_root;
- if !ai_rel then AI_Rel.do_prog !ai_widen_delay prog !ai_root;
+ if !ai_itv then AI_Itv.do_prog !ai_widen_delay (Typing.root_prog prog !ai_root);
+ if !ai_rel then AI_Rel.do_prog !ai_widen_delay (Typing.root_prog prog !ai_root);
if !vtest then do_test_interpret prog true
else if !test then do_test_interpret prog false;