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author | Alex Auvolat <alex.auvolat@ansys.com> | 2014-07-02 10:27:30 +0200 |
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committer | Alex Auvolat <alex.auvolat@ansys.com> | 2014-07-02 10:27:30 +0200 |
commit | 08096254ecf8c2341320e255ad74a7d99fb46d47 (patch) | |
tree | 383b7710c1a82d50a527b367581128f158cc445b /main.ml | |
parent | cbd88f9238dbd66acacb782bdc0fd3aa9a82b804 (diff) | |
download | scade-analyzer-08096254ecf8c2341320e255ad74a7d99fb46d47.tar.gz scade-analyzer-08096254ecf8c2341320e255ad74a7d99fb46d47.zip |
More verbosity ; adapt rfollow so that it can be proved
Diffstat (limited to 'main.ml')
-rw-r--r-- | main.ml | 5 |
1 files changed, 4 insertions, 1 deletions
@@ -31,6 +31,7 @@ let ai_no_time_scopes = ref "" let ai_init_scopes = ref "" let ai_disj_v = ref "" let ai_vci = ref false +let ai_vvci = ref false let ifile = ref "" let usage = "usage: analyzer [options] file.scade" @@ -46,6 +47,7 @@ let options = [ "--ai-itv-edd", Arg.Set ai_itv_edd, "Do abstract analysis using intervals and EDD disjunction domain."; "--ai-rel-edd", Arg.Set ai_rel_edd, "Do abstract analysis using Apron and EDD disjunction domain."; "--ai-vci", Arg.Set ai_vci, "Verbose chaotic iterations (show state at each iteration)"; + "--ai-vvci", Arg.Set ai_vvci, "Very verbose chaotic iterations (show everything all the time)"; "--wd", Arg.Set_int ai_widen_delay, "Widening delay in abstract analysis of loops (default: 3)."; "--root", Arg.Set_string ai_root, "Root node for abstract analysis (default: test)."; "--no-time", Arg.Set_string ai_no_time_scopes, "Scopes for which not to introduce a 'time' variable in analysis."; @@ -117,7 +119,8 @@ let () = let opt = { widen_delay = !ai_widen_delay; disjunct = disj; - verbose_ci = !ai_vci + verbose_ci = !ai_vci; + vverbose_ci = !ai_vvci; } in if !ai_itv then AI_Itv.do_prog opt rp; |