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authorAlex Auvolat <alex.auvolat@ansys.com>2014-06-12 16:48:43 +0200
committerAlex Auvolat <alex.auvolat@ansys.com>2014-06-12 16:48:43 +0200
commit9d280918051a77683fa7b9d15842eead22f7944a (patch)
tree7ea7eb63614acde889c643c48b32134d7c0dc558 /interpret/data.ml
parent68fef7a9612cf42ba42d9ca1cc2423556f66b461 (diff)
downloadscade-analyzer-9d280918051a77683fa7b9d15842eead22f7944a.tar.gz
scade-analyzer-9d280918051a77683fa7b9d15842eead22f7944a.zip
Adopt same output format as test.c
Diffstat (limited to 'interpret/data.ml')
-rw-r--r--interpret/data.ml4
1 files changed, 2 insertions, 2 deletions
diff --git a/interpret/data.ml b/interpret/data.ml
index 2721528..51afcc3 100644
--- a/interpret/data.ml
+++ b/interpret/data.ml
@@ -34,9 +34,9 @@ let get_var (st: state) (c: calc_map) (id: id) : (state * svalue) =
if VarMap.mem id st then st
else try match VarMap.find id c with
| F f ->
- Format.printf "%s[ " id;
+ (* Format.printf "%s[ " id; *)
let r = f (VarMap.add id VBusy st) c in
- Format.printf "]%s " id;
+ (* Format.printf "]%s " id; *)
r
with Not_found -> raise (No_variable id)
in