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authorAlex Auvolat <alex.auvolat@ansys.com>2014-06-26 18:03:33 +0200
committerAlex Auvolat <alex.auvolat@ansys.com>2014-06-26 18:03:33 +0200
commit11e7905ba16d4b13b5c2eda50a198391693e5d96 (patch)
treee083b92f611047eb5ae353aca497021a9611a108 /frontend
parentf3d89408ebb44f77f257b2cb51a4bdd74b9268d0 (diff)
downloadscade-analyzer-11e7905ba16d4b13b5c2eda50a198391693e5d96.tar.gz
scade-analyzer-11e7905ba16d4b13b5c2eda50a198391693e5d96.zip
Minor corrections.
- Use correect clock scope in typing - De-activate multi-valuated domain for enumerate vars + var couples. - Add comment explaining why it doesn't work
Diffstat (limited to 'frontend')
-rw-r--r--frontend/typing.ml4
1 files changed, 2 insertions, 2 deletions
diff --git a/frontend/typing.ml b/frontend/typing.ml
index 167caea..9fe2c8f 100644
--- a/frontend/typing.ml
+++ b/frontend/typing.ml
@@ -121,14 +121,14 @@ let node_vars p f nid =
*)
let clock_vars rp (node, prefix, _) =
let v =
- if not (rp.no_time_scope (node^"/"))
+ if not (rp.no_time_scope (node^"/"^prefix))
then
[
false, node^"/"^prefix^"time", TInt;
false, "N"^node^"/"^prefix^"time", TInt]
else [] in
let v =
- if rp.init_scope (node^"/")
+ if rp.init_scope (node^"/"^prefix)
then
(false, node^"/"^prefix^"init", bool_type)::
(false, "N"^node^"/"^prefix^"init", bool_type)::v