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| author | Alex Auvolat <alex.auvolat@ansys.com> | 2014-07-08 18:03:14 +0200 |
|---|---|---|
| committer | Alex Auvolat <alex.auvolat@ansys.com> | 2014-07-08 18:03:14 +0200 |
| commit | 4ecc11528b3490df5e2b8ea2c602d291b19c6bf0 (patch) | |
| tree | eba009eb4d6023b4a19af0a43298aae98e03dfb7 /frontend/typing.ml | |
| parent | d6db8e934346d3a4ff2bb1470a9512462419bf03 (diff) | |
| download | scade-analyzer-4ecc11528b3490df5e2b8ea2c602d291b19c6bf0.tar.gz scade-analyzer-4ecc11528b3490df5e2b8ea2c602d291b19c6bf0.zip | |
Correct some bugs on clocks.
Diffstat (limited to 'frontend/typing.ml')
| -rw-r--r-- | frontend/typing.ml | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/frontend/typing.ml b/frontend/typing.ml index 883e8e0..83374ed 100644 --- a/frontend/typing.ml +++ b/frontend/typing.ml @@ -136,7 +136,12 @@ let clock_vars rp (node, prefix, _) = then (false, node^"/"^prefix^"init", bool_type)::v else v in - v + let v = + (* root scope is always active *) + if node = "" && prefix = "" + then v + else (false, node^"/"^prefix^"act", bool_type)::v + in v (* extract_all_vars : rooted_prog -> scope -> var list @@ -231,7 +236,9 @@ let root_prog p root no_time_scope init_scope = const_vars; all_vars = [] } in - let root_vars = vars_in_node "" (decls_of_node root_node) in + let root_vars = + (false, "/must_reset", bool_type):: + (vars_in_node "" (decls_of_node root_node)) in let root_clock_vars = clock_vars rp root_scope in { rp with all_vars = root_clock_vars @ |