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authorAlex Auvolat <alex.auvolat@ansys.com>2014-06-18 11:34:36 +0200
committerAlex Auvolat <alex.auvolat@ansys.com>2014-06-18 11:34:36 +0200
commit5ac14cee1bdb9f2ccc40ad6eb1841b5c2ed584d1 (patch)
treec03d6741f565f1ed5a5b27efb2c96a8d9a098581 /abstract/environment_domain.ml
parentf04de3faad13a3904836dd1bd8c334b6634d60a4 (diff)
downloadscade-analyzer-5ac14cee1bdb9f2ccc40ad6eb1841b5c2ed584d1.tar.gz
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Pretty printing.
Diffstat (limited to 'abstract/environment_domain.ml')
-rw-r--r--abstract/environment_domain.ml3
1 files changed, 3 insertions, 0 deletions
diff --git a/abstract/environment_domain.ml b/abstract/environment_domain.ml
index 8b2ee34..6e84c75 100644
--- a/abstract/environment_domain.ml
+++ b/abstract/environment_domain.ml
@@ -3,6 +3,7 @@ open Formula
module type ENVIRONMENT_DOMAIN = sig
type t
+ type itv
(* construction *)
val init : t
@@ -15,6 +16,7 @@ module type ENVIRONMENT_DOMAIN = sig
val rmvar : t -> id -> t
val vars : t -> (id * bool) list
val vbottom : t -> t (* bottom value with same environment *)
+ val var_itv : t -> id -> itv
(* set-theoretic operations *)
val join : t -> t -> t (* union *)
@@ -33,6 +35,7 @@ module type ENVIRONMENT_DOMAIN = sig
(* pretty-printing *)
val print_vars : Format.formatter -> t -> id list -> unit
val print_all : Format.formatter -> t -> unit
+ val print_itv : Format.formatter -> itv -> unit
end