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| author | Alex Auvolat <alex.auvolat@ansys.com> | 2014-06-26 18:03:33 +0200 |
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| committer | Alex Auvolat <alex.auvolat@ansys.com> | 2014-06-26 18:03:33 +0200 |
| commit | 11e7905ba16d4b13b5c2eda50a198391693e5d96 (patch) | |
| tree | e083b92f611047eb5ae353aca497021a9611a108 /abstract/abs_interp_edd.ml | |
| parent | f3d89408ebb44f77f257b2cb51a4bdd74b9268d0 (diff) | |
| download | scade-analyzer-11e7905ba16d4b13b5c2eda50a198391693e5d96.tar.gz scade-analyzer-11e7905ba16d4b13b5c2eda50a198391693e5d96.zip | |
Minor corrections.
- Use correect clock scope in typing
- De-activate multi-valuated domain for enumerate vars + var couples.
- Add comment explaining why it doesn't work
Diffstat (limited to 'abstract/abs_interp_edd.ml')
0 files changed, 0 insertions, 0 deletions