camlsim/test/fulladder_sch.net


1
2
3
4
5
6
7
8
9
10
11
12

INPUT a, b, c
OUTPUT s, r
VAR
  _l_1, _l_3, _l_4, _l_5, a, b, c, r, s
IN
_l_4 = XOR a b
_l_5 = AND _l_4 c
_l_3 = AND a b
_l_1 = XOR a b
s = XOR _l_1 c
r = OR _l_3 _l_5