SystDigit-Projet.git - Projet de Système Digital

	Commit message (Expand)	Author	Age	Files	Lines
*	Changes...	Alex AUVOLAT	2014-01-14	1	-0/+4
*	Minor changes to scheduler.	Alex AUVOLAT	2014-01-14	1	-8/+5
*	Document programs ; better time support in monitor.	Alex AUVOLAT	2014-01-04	1	-2/+3
*	CPU all implemented except missing ALU operations.	Alex AUVOLAT	2014-01-03	1	-0/+4
*	Implement lw/sw/lwr/swr ; optimize simplification pass order ; add comments i...	Alex AUVOLAT	2014-01-03	1	-0/+12
*	Implement jr/jalr/jer/jner/jltr/jler/jltru/jleru ; add simplification to sched.	Alex AUVOLAT	2014-01-02	1	-0/+8
*	Tabs to spaces ; deleted Caml simulator (useless anyways)	Alex AUVOLAT	2013-12-17	1	-284/+284
*	Added optimization pass : delete useless CONCAT's.	Alex AUVOLAT	2013-11-19	1	-1/+56
*	More optimizations.	Alex AUVOLAT	2013-11-08	1	-39/+70
*	Minor changes.	Alex AUVOLAT	2013-11-08	1	-30/+48
*	Deleted useless debug output ; coded working 60/60/24 clock.	Alex AUVOLAT	2013-11-05	1	-5/+0
*	More simplifcation passes...	Alex AUVOLAT	2013-11-05	1	-26/+54
*	Added netlist simplification passes (not yet quite complete !)	Alex AUVOLAT	2013-11-05	1	-0/+214