SystDigit-Projet.git - Projet de Système Digital

	Commit message (Collapse)	Author	Age	Files	Lines
*	Added simulator monitor tool.	Alex AUVOLAT	2014-01-03	1	-0/+1
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*	Started CPU implementation.	Alex AUVOLAT	2014-01-02	1	-1/+1
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*	Tabs to spaces ; deleted Caml simulator (useless anyways)	Alex AUVOLAT	2013-12-17	1	-61/+61
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*	RAM gives result immediately..	Alex AUVOLAT	2013-11-19	1	-3/+7
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*	Added a TODO, changed a few comments.	Alex AUVOLAT	2013-11-15	1	-1/+3
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*	Added ROM support, coded a 24/60/60 watch with output for 7-bit LCD display	Alex AUVOLAT	2013-11-11	1	-3/+14
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*	[WIP] Change dumb netlist format in scheduler and simulator.	Alex AUVOLAT	2013-11-08	1	-41/+34
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*	C simulator quite completed.	Alex AUVOLAT	2013-11-04	1	-6/+16
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*	Added stub C simulator (defined dumb-down syntax for netlists).	Alex AUVOLAT	2013-11-04	1	-0/+116