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-rw-r--r--.gitignore6
-rw-r--r--camlsim/test/clock_div_sch.net9
-rw-r--r--camlsim/test/cm2_sch.net9
-rw-r--r--camlsim/test/fulladder_sch.net12
-rw-r--r--camlsim/test/nadder_sch.net17
-rw-r--r--camlsim/test/ram_sch.net32
-rw-r--r--csim/Makefile2
-rw-r--r--csim/load.c4
-rw-r--r--csim/main.c4
-rw-r--r--sched/test/clock_div.net9
-rw-r--r--sched/test/cm2.net9
-rw-r--r--sched/test/fulladder.net12
-rw-r--r--sched/test/nadder.net17
-rw-r--r--sched/test/ram.net32
-rw-r--r--tests/Makefile18
-rw-r--r--tests/clock_div.mj (renamed from sched/test/clock_div.mj)0
-rw-r--r--tests/cm2.mj (renamed from sched/test/cm2.mj)0
-rw-r--r--tests/fulladder.mj (renamed from sched/test/fulladder.mj)0
-rw-r--r--tests/nadder.mj (renamed from sched/test/nadder.mj)0
-rw-r--r--tests/ram.mj (renamed from sched/test/ram.mj)0
20 files changed, 28 insertions, 164 deletions
diff --git a/.gitignore b/.gitignore
index 9c555fb..7f124fb 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,7 +1,7 @@
+*.swp
*/_build/*
*/*.byte
-sched/test/*_sch.net
-sched/test/*.dumb
-*.swp
csim/csim
*.o
+tests/*.net
+tests/*.dumb
diff --git a/camlsim/test/clock_div_sch.net b/camlsim/test/clock_div_sch.net
deleted file mode 100644
index 0ae5cd9..0000000
--- a/camlsim/test/clock_div_sch.net
+++ /dev/null
@@ -1,9 +0,0 @@
-INPUT
-OUTPUT o
-VAR
- _l_2, c, o
-IN
-_l_2 = REG o
-o = REG c
-c = NOT _l_2
-
diff --git a/camlsim/test/cm2_sch.net b/camlsim/test/cm2_sch.net
deleted file mode 100644
index e9900d5..0000000
--- a/camlsim/test/cm2_sch.net
+++ /dev/null
@@ -1,9 +0,0 @@
-INPUT x
-OUTPUT s, r
-VAR
- _l_1, r, s, x
-IN
-s = REG _l_1
-_l_1 = XOR x s
-r = AND x s
-
diff --git a/camlsim/test/fulladder_sch.net b/camlsim/test/fulladder_sch.net
deleted file mode 100644
index 96fc154..0000000
--- a/camlsim/test/fulladder_sch.net
+++ /dev/null
@@ -1,12 +0,0 @@
-INPUT a, b, c
-OUTPUT s, r
-VAR
- _l_1, _l_3, _l_4, _l_5, a, b, c, r, s
-IN
-_l_4 = XOR a b
-_l_5 = AND _l_4 c
-_l_3 = AND a b
-_l_1 = XOR a b
-s = XOR _l_1 c
-r = OR _l_3 _l_5
-
diff --git a/camlsim/test/nadder_sch.net b/camlsim/test/nadder_sch.net
deleted file mode 100644
index 5602eb4..0000000
--- a/camlsim/test/nadder_sch.net
+++ /dev/null
@@ -1,17 +0,0 @@
-INPUT a, b
-OUTPUT o, c
-VAR
- _l_10_50, _l_11_49, _l_16_22, _l_17_21, _l_7_52, _l_9_51, a, b, c,
- c_n1_27, o, s_n_26
-IN
-_l_17_21 = SELECT 0 b
-_l_16_22 = SELECT 0 a
-c_n1_27 = 0
-_l_10_50 = XOR _l_16_22 _l_17_21
-_l_11_49 = AND _l_10_50 c_n1_27
-_l_9_51 = AND _l_16_22 _l_17_21
-_l_7_52 = XOR _l_16_22 _l_17_21
-s_n_26 = XOR _l_7_52 c_n1_27
-c = OR _l_9_51 _l_11_49
-o = s_n_26
-
diff --git a/camlsim/test/ram_sch.net b/camlsim/test/ram_sch.net
deleted file mode 100644
index 56dda0e..0000000
--- a/camlsim/test/ram_sch.net
+++ /dev/null
@@ -1,32 +0,0 @@
-INPUT ra, we, wa, c
-OUTPUT o
-VAR
- _l_10_22, _l_10_35, _l_10_48, _l_10_61, _l_11_21, _l_11_34, _l_11_47,
- _l_11_60, _l_12_20 : 3, _l_12_33 : 2, _l_12_46 : 1, _l_13_19 : 3, _l_13_32 : 2,
- _l_13_45 : 1, _l_14_18 : 3, _l_14_31 : 2, _l_14_44 : 1, _l_16 : 4,
- _l_9_23, _l_9_36, _l_9_49, _l_9_62, c : 4, o : 4, ra : 2, wa : 2, we
-IN
-_l_13_19 = SLICE 1 3 c
-_l_13_32 = SLICE 1 2 _l_13_19
-_l_13_45 = SLICE 1 1 _l_13_32
-_l_10_61 = SELECT 0 _l_13_45
-o = RAM 2 4 ra we wa _l_16
-_l_12_20 = SLICE 1 3 o
-_l_12_33 = SLICE 1 2 _l_12_20
-_l_12_46 = SLICE 1 1 _l_12_33
-_l_9_62 = SELECT 0 _l_12_46
-_l_11_60 = AND _l_9_62 _l_10_61
-_l_14_44 = _l_11_60
-_l_10_48 = SELECT 0 _l_13_32
-_l_9_49 = SELECT 0 _l_12_33
-_l_11_47 = AND _l_9_49 _l_10_48
-_l_14_31 = CONCAT _l_11_47 _l_14_44
-_l_10_35 = SELECT 0 _l_13_19
-_l_9_36 = SELECT 0 _l_12_20
-_l_11_34 = AND _l_9_36 _l_10_35
-_l_14_18 = CONCAT _l_11_34 _l_14_31
-_l_10_22 = SELECT 0 c
-_l_9_23 = SELECT 0 o
-_l_11_21 = AND _l_9_23 _l_10_22
-_l_16 = CONCAT _l_11_21 _l_14_18
-
diff --git a/csim/Makefile b/csim/Makefile
index 32d100d..c94bee2 100644
--- a/csim/Makefile
+++ b/csim/Makefile
@@ -1,4 +1,4 @@
-main: main.o load.o sim.o
+csim: main.o load.o sim.o
gcc -o csim $^
%.o: %.c
diff --git a/csim/load.c b/csim/load.c
index 05c5f70..a7e6cac 100644
--- a/csim/load.c
+++ b/csim/load.c
@@ -60,6 +60,10 @@ t_program *load_dumb_netlist (FILE *stream) {
p->vars[i].name = malloc(42); // let's bet that the name of a variable will never be longer than 42 chars
fscanf(stream, "%s\n", p->vars[i].name);
+
+ if (p->vars[i].size >= 8*sizeof(t_value)) {
+ fprintf(stderr, "Warning: variable %s might be too big for machine integers.\n", p->vars[i].name);
+ }
}
// read input list
diff --git a/csim/main.c b/csim/main.c
index ad23cd8..a43d7c9 100644
--- a/csim/main.c
+++ b/csim/main.c
@@ -16,7 +16,7 @@ void usage() {
printf ("\nUsage:\n\tcsim [options] <netlist_file>\n\n");
printf("Available options:\n");
printf("\n -rom <file>\n\tLoad a filename as a ROM file for the machine\n");
- printf("\n -n <steps>\n\tOnly run #steps steps of simulation (-1 = infinity)\n");
+ printf("\n -n <steps>\n\tOnly run #steps steps of simulation (0 = infinity)\n");
printf("\n -in <in-file>\n\tRead inputs from given file (eg. named pipe). Defaults to STDIN.\n");
printf("\n -out <out-file>\n\tWrite outputs to given file (eg. named pipe). Defaults to STDOut.\n");
exit(1);
@@ -81,7 +81,7 @@ int main(int argc, char **argv) {
// Run
t_machine *machine = init_machine(program);
i = 0;
- while (i < steps || steps == -1) {
+ while (i < steps || steps == 0) {
read_inputs(machine, input);
machine_step(machine);
write_outputs(machine, output);
diff --git a/sched/test/clock_div.net b/sched/test/clock_div.net
deleted file mode 100644
index 9a17fc7..0000000
--- a/sched/test/clock_div.net
+++ /dev/null
@@ -1,9 +0,0 @@
-INPUT
-OUTPUT o
-VAR
- _l_2, c, o
-IN
-c = NOT _l_2
-o = REG c
-_l_2 = REG o
-
diff --git a/sched/test/cm2.net b/sched/test/cm2.net
deleted file mode 100644
index e296b96..0000000
--- a/sched/test/cm2.net
+++ /dev/null
@@ -1,9 +0,0 @@
-INPUT x
-OUTPUT s, r
-VAR
- _l_1, r, s, x
-IN
-r = AND x s
-s = REG _l_1
-_l_1 = XOR x s
-
diff --git a/sched/test/fulladder.net b/sched/test/fulladder.net
deleted file mode 100644
index b2271c2..0000000
--- a/sched/test/fulladder.net
+++ /dev/null
@@ -1,12 +0,0 @@
-INPUT a, b, c
-OUTPUT s, r
-VAR
- _l_1, _l_3, _l_4, _l_5, a, b, c, r, s
-IN
-r = OR _l_3 _l_5
-s = XOR _l_1 c
-_l_1 = XOR a b
-_l_3 = AND a b
-_l_4 = XOR a b
-_l_5 = AND _l_4 c
-
diff --git a/sched/test/nadder.net b/sched/test/nadder.net
deleted file mode 100644
index bf87051..0000000
--- a/sched/test/nadder.net
+++ /dev/null
@@ -1,17 +0,0 @@
-INPUT a, b
-OUTPUT o, c
-VAR
- _l_10_50, _l_11_49, _l_16_22, _l_17_21, _l_7_52, _l_9_51, a, b, c,
- c_n1_27, o, s_n_26
-IN
-o = s_n_26
-c = OR _l_9_51 _l_11_49
-s_n_26 = XOR _l_7_52 c_n1_27
-_l_7_52 = XOR _l_16_22 _l_17_21
-_l_9_51 = AND _l_16_22 _l_17_21
-_l_10_50 = XOR _l_16_22 _l_17_21
-_l_11_49 = AND _l_10_50 c_n1_27
-c_n1_27 = 0
-_l_16_22 = SELECT 0 a
-_l_17_21 = SELECT 0 b
-
diff --git a/sched/test/ram.net b/sched/test/ram.net
deleted file mode 100644
index 56f2fc6..0000000
--- a/sched/test/ram.net
+++ /dev/null
@@ -1,32 +0,0 @@
-INPUT ra, we, wa, c
-OUTPUT o
-VAR
- _l_10_22, _l_10_35, _l_10_48, _l_10_61, _l_11_21, _l_11_34, _l_11_47,
- _l_11_60, _l_12_20 : 3, _l_12_33 : 2, _l_12_46 : 1, _l_13_19 : 3, _l_13_32 : 2,
- _l_13_45 : 1, _l_14_18 : 3, _l_14_31 : 2, _l_14_44 : 1, _l_16 : 4,
- _l_9_23, _l_9_36, _l_9_49, _l_9_62, c : 4, o : 4, ra : 2, wa : 2, we
-IN
-o = RAM 2 4 ra we wa _l_16
-_l_16 = CONCAT _l_11_21 _l_14_18
-_l_9_23 = SELECT 0 o
-_l_10_22 = SELECT 0 c
-_l_11_21 = OR _l_9_23 _l_10_22
-_l_12_20 = SLICE 1 3 o
-_l_13_19 = SLICE 1 3 c
-_l_14_18 = CONCAT _l_11_34 _l_14_31
-_l_9_36 = SELECT 0 _l_12_20
-_l_10_35 = SELECT 0 _l_13_19
-_l_11_34 = OR _l_9_36 _l_10_35
-_l_12_33 = SLICE 1 2 _l_12_20
-_l_13_32 = SLICE 1 2 _l_13_19
-_l_14_31 = CONCAT _l_11_47 _l_14_44
-_l_9_49 = SELECT 0 _l_12_33
-_l_10_48 = SELECT 0 _l_13_32
-_l_11_47 = OR _l_9_49 _l_10_48
-_l_12_46 = SLICE 1 1 _l_12_33
-_l_13_45 = SLICE 1 1 _l_13_32
-_l_14_44 = _l_11_60
-_l_9_62 = SELECT 0 _l_12_46
-_l_10_61 = SELECT 0 _l_13_45
-_l_11_60 = OR _l_9_62 _l_10_61
-
diff --git a/tests/Makefile b/tests/Makefile
new file mode 100644
index 0000000..443e86a
--- /dev/null
+++ b/tests/Makefile
@@ -0,0 +1,18 @@
+.SECONDARY:
+
+MINIJAZZ=../minijazz/mjc.byte
+SCHED=../sched/main.byte
+SIM=../csim/csim
+
+%.sim: %.dumb
+ $(SIM) $<
+
+%.dumb %_sch.net: %.net
+ $(SCHED) $<
+
+%.net: %.mj
+ $(MINIJAZZ) $<
+
+clean:
+ rm *.net
+ rm *.dumb
diff --git a/sched/test/clock_div.mj b/tests/clock_div.mj
index ad1e919..ad1e919 100644
--- a/sched/test/clock_div.mj
+++ b/tests/clock_div.mj
diff --git a/sched/test/cm2.mj b/tests/cm2.mj
index 8863bf1..8863bf1 100644
--- a/sched/test/cm2.mj
+++ b/tests/cm2.mj
diff --git a/sched/test/fulladder.mj b/tests/fulladder.mj
index c4b6b0e..c4b6b0e 100644
--- a/sched/test/fulladder.mj
+++ b/tests/fulladder.mj
diff --git a/sched/test/nadder.mj b/tests/nadder.mj
index 0c95386..0c95386 100644
--- a/sched/test/nadder.mj
+++ b/tests/nadder.mj
diff --git a/sched/test/ram.mj b/tests/ram.mj
index 5bd4f29..5bd4f29 100644
--- a/sched/test/ram.mj
+++ b/tests/ram.mj
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-21 21:24:10 +0000