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authorAlex AUVOLAT <alex.auvolat@ens.fr>2014-01-03 22:43:07 +0100
committerAlex AUVOLAT <alex.auvolat@ens.fr>2014-01-03 22:43:07 +0100
commit1847bba4d356264268116d7d0b313b86e0af7c5b (patch)
tree78ed2fb08ce6f3534ca00afefb6fdc0588a5c97c /sched
parent1b32dfecc4fd1c9d9d024bb053c43ea17021cc65 (diff)
downloadSystDigit-Projet-1847bba4d356264268116d7d0b313b86e0af7c5b.tar.gz
SystDigit-Projet-1847bba4d356264268116d7d0b313b86e0af7c5b.zip
CPU all implemented except missing ALU operations.
Diffstat (limited to 'sched')
-rw-r--r--sched/simplify.ml4
1 files changed, 4 insertions, 0 deletions
diff --git a/sched/simplify.ml b/sched/simplify.ml
index c68fe66..86c4790 100644
--- a/sched/simplify.ml
+++ b/sched/simplify.ml
@@ -143,6 +143,10 @@ let arith_simplify p =
Earg(Aconst(Array.make sz false))
| Ebinop(_, Avar(a), Avar(b)) when a = b ->
Earg(Avar(a))
+
+ | Emux(_, a, b) when a = b -> Earg(a)
+ | Emux(Aconst[|false|], a, b) -> Earg(a)
+ | Emux(Aconst[|true|], a, b) -> Earg(b)
| Eslice(i, j, k) when i = j -> Eselect(i, k)