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| author | Alex AUVOLAT <alex.auvolat@ens.fr> | 2013-11-04 22:05:57 +0100 |
|---|---|---|
| committer | Alex AUVOLAT <alex.auvolat@ens.fr> | 2013-11-04 22:05:57 +0100 |
| commit | cebd07b64f1f537c5ecf00ec21ff4b7c4032f0a3 (patch) | |
| tree | 9d2048313fe3ad4c92865c8f0236bed24e64449b /sched/test/fulladder_sch.net | |
| parent | f253f98136def21b5e50c5922246e2ddfe315442 (diff) | |
| download | SystDigit-Projet-cebd07b64f1f537c5ecf00ec21ff4b7c4032f0a3.tar.gz SystDigit-Projet-cebd07b64f1f537c5ecf00ec21ff4b7c4032f0a3.zip | |
Added stub C simulator (defined dumb-down syntax for netlists).
Diffstat (limited to 'sched/test/fulladder_sch.net')
| -rw-r--r-- | sched/test/fulladder_sch.net | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/sched/test/fulladder_sch.net b/sched/test/fulladder_sch.net new file mode 100644 index 0000000..96fc154 --- /dev/null +++ b/sched/test/fulladder_sch.net @@ -0,0 +1,12 @@ +INPUT a, b, c +OUTPUT s, r +VAR + _l_1, _l_3, _l_4, _l_5, a, b, c, r, s +IN +_l_4 = XOR a b +_l_5 = AND _l_4 c +_l_3 = AND a b +_l_1 = XOR a b +s = XOR _l_1 c +r = OR _l_3 _l_5 + |