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authorAlex AUVOLAT <alex.auvolat@ens.fr>2014-01-02 22:30:11 +0100
committerAlex AUVOLAT <alex.auvolat@ens.fr>2014-01-02 22:30:11 +0100
commit85bc61cb7fa8f4b9af78064cb65fbad49a109d5f (patch)
tree5116b1c423864f3cde8f1002b7a4dabb62e88fff /cpu/netlist_gen.mli
parent4e1aaf316457f4d4f045fd3ebe500cd70f6bafcc (diff)
downloadSystDigit-Projet-85bc61cb7fa8f4b9af78064cb65fbad49a109d5f.tar.gz
SystDigit-Projet-85bc61cb7fa8f4b9af78064cb65fbad49a109d5f.zip
Started CPU implementation.
Diffstat (limited to 'cpu/netlist_gen.mli')
-rw-r--r--cpu/netlist_gen.mli5
1 files changed, 5 insertions, 0 deletions
diff --git a/cpu/netlist_gen.mli b/cpu/netlist_gen.mli
index 3d40477..280ee8c 100644
--- a/cpu/netlist_gen.mli
+++ b/cpu/netlist_gen.mli
@@ -7,6 +7,9 @@ val id : string -> Netlist_ast.ident
val get : Netlist_ast.ident -> t
val loop : int -> (t * (t -> t))
+val ignore: t -> t -> t (* ignores first value *)
+val ( ^. ) : t -> t -> t (* ignores first value *)
+
val const : string -> t
val ( ++ ) : t -> t -> t (* concat *)
@@ -25,8 +28,10 @@ val ( ** ) : t -> int -> t (* select *)
val ( % ) : t -> int * int -> t (* slice *)
val rom : string -> int -> int -> t -> t
+ (* addr_size, word_size, read_addr *)
val ram : int -> int -> t -> t -> t -> t -> t
+ (* addr_size, word_size, read_addr, write_enable, write_addr, data *)
val reg : int -> t -> t