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authorAlex AUVOLAT <alex.auvolat@ens.fr>2014-01-02 19:21:04 +0100
committerAlex AUVOLAT <alex.auvolat@ens.fr>2014-01-02 19:21:04 +0100
commit4e1aaf316457f4d4f045fd3ebe500cd70f6bafcc (patch)
treee9907c38424f1b3e727a8f661a0d9eb611d7cbaa /cpu/example_cpu.ml
parent6fdfebbc65949d6ad55ee5a47bd6b5bdbc74a91f (diff)
downloadSystDigit-Projet-4e1aaf316457f4d4f045fd3ebe500cd70f6bafcc.tar.gz
SystDigit-Projet-4e1aaf316457f4d4f045fd3ebe500cd70f6bafcc.zip
Renamed example cpu file
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+open Netlist_gen
+
+(* Dumb CPU that just does an 8-bit addition *)
+
+let sumz n i =
+ let x, set_x = loop n in
+ let r = reg n x in
+ let o1, o2 = Alu.nadder n i r (const "0") in
+ set_x o1, o2
+
+let p =
+ let width = 16 in
+ let sum, r = sumz width (get "in") in
+ program
+ [ "in", width ]
+ [ "out", width, sum;
+ "r", 1, r ]
+
+let () = Netlist_gen.print stdout p