summaryrefslogtreecommitdiff
path: root/cpu/cpu.ml
diff options
context:
space:
mode:
authorAlex AUVOLAT <alex.auvolat@ens.fr>2014-02-05 10:57:29 +0100
committerAlex AUVOLAT <alex.auvolat@ens.fr>2014-02-05 10:57:29 +0100
commitfca182dc38648a1b7ef31d6d56cbdd5ff00bb685 (patch)
treece2d9ed366fe39877a27afa0e23148a59bbee1a4 /cpu/cpu.ml
parenta6f850587a844bb3c8894ed542bbad4e143e6dac (diff)
downloadSystDigit-Projet-fca182dc38648a1b7ef31d6d56cbdd5ff00bb685.tar.gz
SystDigit-Projet-fca182dc38648a1b7ef31d6d56cbdd5ff00bb685.zip
Change processor initial date.HEADmaster
Diffstat (limited to 'cpu/cpu.ml')
-rw-r--r--cpu/cpu.ml10
1 files changed, 4 insertions, 6 deletions
diff --git a/cpu/cpu.ml b/cpu/cpu.ml
index 867a979..7b7b580 100644
--- a/cpu/cpu.ml
+++ b/cpu/cpu.ml
@@ -135,16 +135,14 @@ let rl, rh, i, ex, exf, pc =
let ram_read, save_ram_read = loop 8 in
(* Read instruction low when read is set and instruction high on next tick *)
- let next_read_ihi, save_next_read_ihi = loop 1 in
- let read_ihi = reg 1 next_read_ihi in
let read_ilow = read in
+ let read_ihi = reg 1 read_ilow in
let ra = mux read_ilow ra pc in
- let ilow = reg 8 (mux read_ilow (zeroes 8) ram_read) in
+ let ilow = reg 8 ram_read in
let ra = mux read_ihi ra (nadder 16 pc (one 16)) in
- let ihi = mux read_ihi (zeroes 8) ram_read in
+ let ihi = ram_read in
- let read_ilow = save_next_read_ihi read_ilow in
(* When execution has just been read, exec is true, and exec is false the rest of the time *)
let exec = read_ihi in
(* Keep same instruction in register until new instruction is read *)
@@ -212,7 +210,7 @@ let rl, rh, i, ex, exf, pc =
let instr_jal = exec ^& eq_c 5 i_i 0b01001 in
let next_pc = mux instr_jal next_pc (nadder 16 pc (sign_extend 11 16 i_jd)) in
let instr_jalxx = instr_jal in
- (* instruction : jr/jalr/jer/jner/jltr/jler/jltru/ljeru *)
+ (* instruction : jr/jalr/jer/jner/jltr/jler/jltru/jleru *)
let instr_jxxr = exec ^& eq_c 4 (i_i % (1, 4)) 0b0101 in
let f0 = i_i ** 0 in
let instr_jr = (not f0) ^& (eq_c 2 i_f 0) in