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| author | Alex AUVOLAT <alex.auvolat@ens.fr> | 2014-01-02 22:30:11 +0100 |
|---|---|---|
| committer | Alex AUVOLAT <alex.auvolat@ens.fr> | 2014-01-02 22:30:11 +0100 |
| commit | 85bc61cb7fa8f4b9af78064cb65fbad49a109d5f (patch) | |
| tree | 5116b1c423864f3cde8f1002b7a4dabb62e88fff /cpu/Makefile | |
| parent | 4e1aaf316457f4d4f045fd3ebe500cd70f6bafcc (diff) | |
| download | SystDigit-Projet-85bc61cb7fa8f4b9af78064cb65fbad49a109d5f.tar.gz SystDigit-Projet-85bc61cb7fa8f4b9af78064cb65fbad49a109d5f.zip | |
Started CPU implementation.
Diffstat (limited to 'cpu/Makefile')
| -rw-r--r-- | cpu/Makefile | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/cpu/Makefile b/cpu/Makefile index 74bfbae..1ab6397 100644 --- a/cpu/Makefile +++ b/cpu/Makefile @@ -3,10 +3,11 @@ GENERATOR=netlist_ast.ml netlist_gen.ml netlist_gen.mli AUXILLARY=alu.ml -SCHED=../sched/main.byte +SCHED=../sched/main.native SIM=../csim/csim -all: cpu_opt.sim +all: _build/cpu_opt.dumb + $(SIM) -rom ROM0 prog_rom0.rom $< %.sim: _build/%.dumb $(SIM) $< |