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authorAlex AUVOLAT <alex.auvolat@ens.fr>2013-10-31 18:15:01 +0100
committerAlex AUVOLAT <alex.auvolat@ens.fr>2013-10-31 18:15:01 +0100
commitf253f98136def21b5e50c5922246e2ddfe315442 (patch)
tree5ba21cf7a697bccaf58bf8072cb4c283be85a84e /camlsim/test/ram_sch.net
parent0b269f32dd9b8d349f94793dad44e728473e9f0a (diff)
downloadSystDigit-Projet-f253f98136def21b5e50c5922246e2ddfe315442.tar.gz
SystDigit-Projet-f253f98136def21b5e50c5922246e2ddfe315442.zip
Simulator started.
Diffstat (limited to 'camlsim/test/ram_sch.net')
-rw-r--r--camlsim/test/ram_sch.net32
1 files changed, 32 insertions, 0 deletions
diff --git a/camlsim/test/ram_sch.net b/camlsim/test/ram_sch.net
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+++ b/camlsim/test/ram_sch.net
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+INPUT ra, we, wa, c
+OUTPUT o
+VAR
+ _l_10_22, _l_10_35, _l_10_48, _l_10_61, _l_11_21, _l_11_34, _l_11_47,
+ _l_11_60, _l_12_20 : 3, _l_12_33 : 2, _l_12_46 : 1, _l_13_19 : 3, _l_13_32 : 2,
+ _l_13_45 : 1, _l_14_18 : 3, _l_14_31 : 2, _l_14_44 : 1, _l_16 : 4,
+ _l_9_23, _l_9_36, _l_9_49, _l_9_62, c : 4, o : 4, ra : 2, wa : 2, we
+IN
+_l_13_19 = SLICE 1 3 c
+_l_13_32 = SLICE 1 2 _l_13_19
+_l_13_45 = SLICE 1 1 _l_13_32
+_l_10_61 = SELECT 0 _l_13_45
+o = RAM 2 4 ra we wa _l_16
+_l_12_20 = SLICE 1 3 o
+_l_12_33 = SLICE 1 2 _l_12_20
+_l_12_46 = SLICE 1 1 _l_12_33
+_l_9_62 = SELECT 0 _l_12_46
+_l_11_60 = AND _l_9_62 _l_10_61
+_l_14_44 = _l_11_60
+_l_10_48 = SELECT 0 _l_13_32
+_l_9_49 = SELECT 0 _l_12_33
+_l_11_47 = AND _l_9_49 _l_10_48
+_l_14_31 = CONCAT _l_11_47 _l_14_44
+_l_10_35 = SELECT 0 _l_13_19
+_l_9_36 = SELECT 0 _l_12_20
+_l_11_34 = AND _l_9_36 _l_10_35
+_l_14_18 = CONCAT _l_11_34 _l_14_31
+_l_10_22 = SELECT 0 c
+_l_9_23 = SELECT 0 o
+_l_11_21 = AND _l_9_23 _l_10_22
+_l_16 = CONCAT _l_11_21 _l_14_18
+