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| author | Alex AUVOLAT <alex.auvolat@ens.fr> | 2013-10-31 18:15:01 +0100 |
|---|---|---|
| committer | Alex AUVOLAT <alex.auvolat@ens.fr> | 2013-10-31 18:15:01 +0100 |
| commit | f253f98136def21b5e50c5922246e2ddfe315442 (patch) | |
| tree | 5ba21cf7a697bccaf58bf8072cb4c283be85a84e /camlsim/test/nadder_sch.net | |
| parent | 0b269f32dd9b8d349f94793dad44e728473e9f0a (diff) | |
| download | SystDigit-Projet-f253f98136def21b5e50c5922246e2ddfe315442.tar.gz SystDigit-Projet-f253f98136def21b5e50c5922246e2ddfe315442.zip | |
Simulator started.
Diffstat (limited to 'camlsim/test/nadder_sch.net')
| -rw-r--r-- | camlsim/test/nadder_sch.net | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/camlsim/test/nadder_sch.net b/camlsim/test/nadder_sch.net new file mode 100644 index 0000000..5602eb4 --- /dev/null +++ b/camlsim/test/nadder_sch.net @@ -0,0 +1,17 @@ +INPUT a, b +OUTPUT o, c +VAR + _l_10_50, _l_11_49, _l_16_22, _l_17_21, _l_7_52, _l_9_51, a, b, c, + c_n1_27, o, s_n_26 +IN +_l_17_21 = SELECT 0 b +_l_16_22 = SELECT 0 a +c_n1_27 = 0 +_l_10_50 = XOR _l_16_22 _l_17_21 +_l_11_49 = AND _l_10_50 c_n1_27 +_l_9_51 = AND _l_16_22 _l_17_21 +_l_7_52 = XOR _l_16_22 _l_17_21 +s_n_26 = XOR _l_7_52 c_n1_27 +c = OR _l_9_51 _l_11_49 +o = s_n_26 + |