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authorAlex AUVOLAT <alex.auvolat@ens.fr>2014-01-03 22:50:46 +0100
committerAlex AUVOLAT <alex.auvolat@ens.fr>2014-01-03 22:50:46 +0100
commit2392043f5e44af97a8d84d05fa02c13ece0adcb0 (patch)
treeb51dd89955091e72d10f6df129968709ac1e847b
parent6543be77b37ad7626d4a4b1a368f6fcbafc89b24 (diff)
downloadSystDigit-Projet-2392043f5e44af97a8d84d05fa02c13ece0adcb0.tar.gz
SystDigit-Projet-2392043f5e44af97a8d84d05fa02c13ece0adcb0.zip
Corrected serial mmio
-rw-r--r--cpu/cpu.ml2
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/cpu.ml b/cpu/cpu.ml
index e47c0c8..23c0875 100644
--- a/cpu/cpu.ml
+++ b/cpu/cpu.ml
@@ -54,7 +54,7 @@ let cpu_ram ra we wa d =
let ser_busy = nonnull 8 ser in
let read_data =
set_ser_in_busy ser_busy ^.
- set_next_ser ser ^.
+ set_next_ser (mux read_ser ser (zeroes 8)) ^.
mux read_ser read_data ser in
set_dbg_ra ra ^.