SystDigit-Projet.git - Projet de Système Digital

	Commit message (Collapse)	Author	Age	Files	Lines
*	Document programs ; better time support in monitor.	Alex AUVOLAT	2014-01-04	3	-8/+16
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*	Added simulator monitor tool.	Alex AUVOLAT	2014-01-03	1	-1/+1
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*	Started CPU implementation.	Alex AUVOLAT	2014-01-02	2	-2/+2
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*	Minor changes.	Alex AUVOLAT	2013-11-12	1	-0/+78
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*	Corrected a stupid bug.	Alex AUVOLAT	2013-11-11	1	-1/+1
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*	Added ROM support, coded a 24/60/60 watch with output for 7-bit LCD display	Alex AUVOLAT	2013-11-11	3	-0/+129
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*	More optimizations.	Alex AUVOLAT	2013-11-08	1	-2/+4
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*	Minor changes.	Alex AUVOLAT	2013-11-08	1	-0/+1
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*	Simulator fixed.	Alex AUVOLAT	2013-11-08	2	-3/+3
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*	[WIP] Change dumb netlist format in scheduler and simulator.	Alex AUVOLAT	2013-11-08	1	-2/+2
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*	Documented the C simulator in the README file ; added a test file.	Alex AUVOLAT	2013-11-06	1	-0/+62
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*	Deleted useless debug output ; coded working 60/60/24 clock.	Alex AUVOLAT	2013-11-05	1	-7/+14
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*	More simplifcation passes...	Alex AUVOLAT	2013-11-05	2	-20/+19
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*	Added netlist simplification passes (not yet quite complete !)	Alex AUVOLAT	2013-11-05	2	-6/+75
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*	Reorganized folders.	Alex AUVOLAT	2013-11-05	6	-0/+64