SystDigit-Projet.git - Projet de Système Digital

	Commit message (Collapse)	Author	Age	Files	Lines
*	Added simulator monitor tool.	Alex AUVOLAT	2014-01-03	1	-1/+1
\|
*	Started CPU implementation.	Alex AUVOLAT	2014-01-02	2	-2/+2
\|
*	Minor changes.	Alex AUVOLAT	2013-11-12	1	-0/+78
\|
*	Corrected a stupid bug.	Alex AUVOLAT	2013-11-11	1	-1/+1
\|
*	Added ROM support, coded a 24/60/60 watch with output for 7-bit LCD display	Alex AUVOLAT	2013-11-11	3	-0/+129
\|
*	More optimizations.	Alex AUVOLAT	2013-11-08	1	-2/+4
\|
*	Minor changes.	Alex AUVOLAT	2013-11-08	1	-0/+1
\|
*	Simulator fixed.	Alex AUVOLAT	2013-11-08	2	-3/+3
\|
*	[WIP] Change dumb netlist format in scheduler and simulator.	Alex AUVOLAT	2013-11-08	1	-2/+2
\|
*	Documented the C simulator in the README file ; added a test file.	Alex AUVOLAT	2013-11-06	1	-0/+62
\|
*	Deleted useless debug output ; coded working 60/60/24 clock.	Alex AUVOLAT	2013-11-05	1	-7/+14
\|
*	More simplifcation passes...	Alex AUVOLAT	2013-11-05	2	-20/+19
\|
*	Added netlist simplification passes (not yet quite complete !)	Alex AUVOLAT	2013-11-05	2	-6/+75
\|
*	Reorganized folders.	Alex AUVOLAT	2013-11-05	6	-0/+64