SystDigit-Projet.git - Projet de Système Digital

	Commit message (Collapse)	Author	Age	Files	Lines
*	Nothing.	Alex AUVOLAT	2014-01-03	1	-1/+1
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*	CPU all implemented except missing ALU operations.	Alex AUVOLAT	2014-01-03	3	-33/+175
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*	Monitor now works correctly.	Alex AUVOLAT	2014-01-03	2	-6/+9
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*	Added simulator monitor tool.	Alex AUVOLAT	2014-01-03	3	-27/+91
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*	Implement lw/sw/lwr/swr ; optimize simplification pass order ; add comments ↵	Alex AUVOLAT	2014-01-03	3	-14/+46
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*	Implement jr/jalr/jer/jner/jltr/jler/jltru/jleru ; add simplification to sched.	Alex AUVOLAT	2014-01-02	2	-16/+76
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*	CPU runs a simple program that increments A and loops (all other ↵	Alex AUVOLAT	2014-01-02	1	-16/+20
\| \| \| \|	instructions unimplemented)
*	Started CPU implementation.	Alex AUVOLAT	2014-01-02	6	-71/+270
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*	Renamed example cpu file	Alex AUVOLAT	2014-01-02	1	-0/+0
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*	New netlist generation protocol	Alex AUVOLAT	2014-01-02	5	-3497/+276
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*	Memorizing CPU : summs all the entries	Alex AUVOLAT	2014-01-02	1	-1/+8
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*	Ajout support pour les cycles.	Alex AUVOLAT	2014-01-02	3	-630/+1910
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*	Premiers morceaux de CPU - enfin non, rien du tout...	Alex AUVOLAT	2013-12-19	7	-0/+2325