SystDigit-Projet.git - Projet de Système Digital

	Commit message (Collapse)	Author	Age	Files	Lines
*	Document.	Alex AUVOLAT	2014-01-07	1	-1/+3
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*	Make sw/sb run in one tick less, correct scheduler.	Alex AUVOLAT	2014-01-06	1	-9/+9
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*	Style corrections.	Alex AUVOLAT	2014-01-03	1	-12/+12
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*	Corrected serial mmio	Alex AUVOLAT	2014-01-03	1	-1/+1
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*	CPU all implemented except missing ALU operations.	Alex AUVOLAT	2014-01-03	1	-24/+60
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*	Added simulator monitor tool.	Alex AUVOLAT	2014-01-03	1	-16/+72
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*	Implement lw/sw/lwr/swr ; optimize simplification pass order ; add comments ↵	Alex AUVOLAT	2014-01-03	1	-11/+43
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*	Implement jr/jalr/jer/jner/jltr/jler/jltru/jleru ; add simplification to sched.	Alex AUVOLAT	2014-01-02	1	-4/+20
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*	CPU runs a simple program that increments A and loops (all other ↵	Alex AUVOLAT	2014-01-02	1	-16/+20
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*	Started CPU implementation.	Alex AUVOLAT	2014-01-02	1	-0/+157
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*	Renamed example cpu file	Alex AUVOLAT	2014-01-02	1	-19/+0
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*	New netlist generation protocol	Alex AUVOLAT	2014-01-02	1	-7/+11
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*	Memorizing CPU : summs all the entries	Alex AUVOLAT	2014-01-02	1	-1/+8
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*	Premiers morceaux de CPU - enfin non, rien du tout...	Alex AUVOLAT	2013-12-19	1	-0/+8