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-rw-r--r--cpu/cpu.ml41
1 files changed, 27 insertions, 14 deletions
diff --git a/cpu/cpu.ml b/cpu/cpu.ml
index b7e394b..78caa30 100644
--- a/cpu/cpu.ml
+++ b/cpu/cpu.ml
@@ -6,6 +6,8 @@ let ser_in_busy, save_ser_in_busy = loop 1
let dbg_ra, save_dbg_ra = loop 16
let dbg_read_data, save_dbg_read_data = loop 8
+let dbg_wa, save_dbg_wa = loop 16
+let dbg_write_data, save_dbg_write_data = loop 8
let cpu_ram ra we wa d =
(* Ram chip has word size = 8 bits and address size = 16 bits
@@ -54,6 +56,7 @@ let cpu_ram ra we wa d =
let iser = nonnull 8 ser_in in
let ser = mux iser ser ser_in in
let ser_busy = nonnull 8 ser in
+ let ser_busy = mux read_ser ser_busy (const "0") in
let read_data =
save_ser_in_busy ser_busy ^.
save_next_ser (mux read_ser ser (zeroes 8)) ^.
@@ -61,6 +64,8 @@ let cpu_ram ra we wa d =
save_dbg_ra ra ^.
save_dbg_read_data read_data ^.
+ save_dbg_wa wa ^.
+ save_dbg_write_data d ^.
read_data
@@ -149,18 +154,18 @@ let rl, rh, i, ex, exf, pc =
(* instruction : add/sub/mul/div/unsigned/or/and/xor/nor/lsl/lsr/asr *)
let instr_alu = eq_c 3 (i_i % (2, 4)) 0b000 in
- let f0 = i_i ** 0 in
let f1 = i_i ** 1 in
+ let f0 = i_i ** 0 in
let double_instr_alu = instr_alu ^& (not f1) ^& (i_f ** 1) ^& (ne_n 3 i_r (const "101")) in
- let instr_alu = exec ^& instr_alu in
- let instr_alu_2 = reg 1 (exec ^& double_instr_alu) in
- let alu_d1, alu_d2 = alu f1 f0 i_f v_ra v_rb in
- let wr = mux instr_alu wr i_r in
- let rwd = mux instr_alu rwd alu_d1 in
- let wr = mux instr_alu_2 wr (const "101") in
- let rwd = mux instr_alu_2 rwd alu_d2 in
- let exec_finished = mux double_instr_alu exec_finished instr_alu_2 in
+ let alu_d1, alu_d2, instr_alu_finished = alu f1 f0 i_f v_ra v_rb (exec ^& instr_alu) in
+ let instr_alu_store_2 = reg 1 (instr_alu_finished ^& double_instr_alu) in
+ let wr = mux instr_alu_finished wr i_r in
+ let rwd = mux instr_alu_finished rwd alu_d1 in
+ let wr = mux instr_alu_store_2 wr (const "101") in
+ let rwd = mux instr_alu_store_2 rwd alu_d2 in
+ let exec_finished = mux instr_alu exec_finished
+ (mux double_instr_alu instr_alu_finished instr_alu_store_2) in
(* instruction : se/sne/slt/slte/sleu/sleu *)
@@ -183,6 +188,7 @@ let rl, rh, i, ex, exf, pc =
let instr_j = exec ^& eq_c 5 i_i 0b01000 in
let next_pc = mux instr_j next_pc (nadder 16 pc (sign_extend 11 16 i_jd)) in
(* instruction : jal *)
+ let link_pc = next_pc in
let instr_jal = exec ^& eq_c 5 i_i 0b01001 in
let next_pc = mux instr_jal next_pc (nadder 16 pc (sign_extend 11 16 i_jd)) in
let instr_jalxx = instr_jal in
@@ -196,7 +202,7 @@ let rl, rh, i, ex, exf, pc =
let next_pc = mux cond_jxxr next_pc v_r in
(* prologue for jal/jalr *)
let wr = mux instr_jalxx wr (const "011") in
- let rwd = mux instr_jalxx rwd next_pc in
+ let rwd = mux instr_jalxx rwd link_pc in
(* instruction : lra *)
let instr_lra = exec ^& eq_c 5 i_i 0b01100 in
@@ -272,6 +278,11 @@ let rl, rh, i, ex, exf, pc =
( (* lil *) i_id ++ (mux instr_lixz (v_r % (8, 15)) (zeroes 8)))
( (* liu *) (mux instr_lixz (v_r % (0, 7)) (zeroes 8)) ++ i_id)) in
+ (* instruction : lie *)
+ let instr_lie = eq_c 5 i_i 0b11100 in
+ let wr = mux instr_lie wr i_r in
+ let rwd= mux instr_lie rwd (sign_extend 8 16 i_id) in
+
save_cpu_regs wr rwd ^.
save_ram_read (cpu_ram ra we wa d) ^.
save_next_read exec_finished ^.
@@ -287,11 +298,13 @@ let p =
[
"read_ilow", 1, rl;
"read_ihi", 1, rh;
- "exec_instr", 1, ex;
- "exec_finished", 1, exf;
- "instruction", 16, i;
+ "ex_instr", 1, ex;
+ "ex_finish", 1, exf;
+ "i", 16, i;
"ra", 16, dbg_ra;
"read_data", 8, dbg_read_data;
+ "wa", 16, dbg_wa;
+ "write_data", 8, dbg_write_data;
"pc", 16, pc;
"r0_Z", 16, r0;
"r1_A", 16, r1;
@@ -305,5 +318,5 @@ let p =
"ser_in_busy", 1, ser_in_busy;
]
-let () = Netlist_gen.print stdout p
+let () = Netlist_printer.print_program stdout p