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-rw-r--r--README5
-rw-r--r--csim/load.c10
-rw-r--r--csim/sim.c13
-rw-r--r--csim/sim.h10
-rw-r--r--csim/util.c2
-rw-r--r--sched/netlist_dumb.ml50
6 files changed, 48 insertions, 42 deletions
diff --git a/README b/README
index 1570c9d..bbbc454 100644
--- a/README
+++ b/README
@@ -163,7 +163,7 @@ This is the description of the format currently used by the C simulator.
<register destination variable> <register source variable>
<ram list size>
[for each ram]
- <destination variable> <addr size> <word size> <read addr var>
+ <addr size> <word size>
<write enable var> <write addr var> <data var>
<equation list size>
[for each equation]
@@ -180,6 +180,7 @@ ID DESCR ARGS
5 Concat var_a var_b
6 Slice begin end var_id
7 Select number var_id
+8 RAM Read ram_number var_id
Operators :
0 OR
@@ -248,8 +249,6 @@ TODO
----
- More advanced commands for the simulator (cf Jonathan's simulator)
-- RAM reads give result immediately
-- Optimisation : SELECT/SLICE a variable which is a CONCAT
NEXT STEPS
----------
diff --git a/csim/load.c b/csim/load.c
index e6fcf29..607e0e2 100644
--- a/csim/load.c
+++ b/csim/load.c
@@ -84,11 +84,10 @@ t_program *load_dumb_netlist (FILE *stream) {
fscanf(stream, "%d", &(p->n_rams));
p->rams = malloc(p->n_rams * sizeof(t_ram));
for (i = 0; i < p->n_rams; i++) {
- fscanf(stream, "%d %d %d %d %d %d %d\n",
- &(p->rams[i].dest),
+ fscanf(stream, "%d %d %d %d %d\n",
&(p->rams[i].addr_size),
&(p->rams[i].word_size),
- &(p->rams[i].read_addr), &(p->rams[i].write_enable),
+ &(p->rams[i].write_enable),
&(p->rams[i].write_addr), &(p->rams[i].data));
}
@@ -156,6 +155,11 @@ t_program *load_dumb_netlist (FILE *stream) {
&(p->eqs[i].Select.i),
&(p->eqs[i].Select.source));
break;
+ case C_READRAM:
+ fscanf(stream, "%d %d ",
+ &(p->eqs[i].ReadRAM.ram_id),
+ &(p->eqs[i].ReadRAM.source));
+ break;
}
}
diff --git a/csim/sim.c b/csim/sim.c
index db2c736..db30ea3 100644
--- a/csim/sim.c
+++ b/csim/sim.c
@@ -90,15 +90,6 @@ void machine_step(t_machine *m) {
p->vars[p->regs[i].dest].name,
m->reg_data[i]);
}
- for (i = 0; i < p->n_rams; i++) {
- e = m->var_values[p->rams[i].write_enable];
- if (e == 0) {
- a = m->var_values[p->rams[i].read_addr];
- b = m->ram_data[i][a];
- m->var_values[p->rams[i].dest] = b;
- if (DEBUG) fprintf(stderr, "Read ram %lx = %lx\n", a, b);
- }
- }
// DO THE LOGIC
for (i = 0; i < p->n_eqs; i++) {
@@ -167,6 +158,10 @@ void machine_step(t_machine *m) {
if (DEBUG) fprintf(stderr, "select %d %lx->%lx .. ",
p->eqs[i].Select.i, a, v);
break;
+ case C_READRAM:
+ a = m->var_values[p->eqs[i].ReadRAM.source];
+ v = m->ram_data[p->eqs[i].ReadRAM.ram_id][a];
+ if (DEBUG) fprintf(stderr, "Read ram %lx = %lx\n", a, v);
}
m->var_values[p->eqs[i].dest_var] = v & (p->vars[p->eqs[i].dest_var].mask);
if (DEBUG) fprintf(stderr, "%s &%lx : %lx\n",
diff --git a/csim/sim.h b/csim/sim.h
index d77465a..80fab56 100644
--- a/csim/sim.h
+++ b/csim/sim.h
@@ -12,6 +12,7 @@
#define C_CONCAT 5
#define C_SLICE 6
#define C_SELECT 7
+#define C_READRAM 8
// Binary operators
#define OP_OR 0
@@ -45,9 +46,8 @@ typedef struct {
} t_reg;
typedef struct {
- t_id dest;
int addr_size, word_size;
- t_id read_addr, write_enable, write_addr, data;
+ t_id write_enable, write_addr, data;
} t_ram;
typedef struct {
@@ -83,6 +83,10 @@ typedef struct {
int i;
t_id source;
} Select;
+ struct {
+ int ram_id;
+ t_id source;
+ } ReadRAM;
};
} t_equation;
@@ -127,6 +131,6 @@ void write_outputs(t_machine *m, FILE *stream);
// Implemented in util.c
int pow2(int exp);
t_value read_bool(FILE *stream, t_value *mask);
-int is_prefix(char *prefix, char *str);
+int is_prefix(const char *prefix, const char *str);
#endif
diff --git a/csim/util.c b/csim/util.c
index ef0ae32..c815e8e 100644
--- a/csim/util.c
+++ b/csim/util.c
@@ -35,7 +35,7 @@ t_value read_bool(FILE *stream, t_value *mask) {
return r;
}
-int is_prefix(char *prefix, char *str) {
+int is_prefix(const char *prefix, const char *str) {
while (*prefix) {
if (*prefix != *str) return 0;
prefix++;
diff --git a/sched/netlist_dumb.ml b/sched/netlist_dumb.ml
index f16f763..01c187b 100644
--- a/sched/netlist_dumb.ml
+++ b/sched/netlist_dumb.ml
@@ -15,9 +15,9 @@ type const_val = bool array
(* keep type binop from netlist_ast *)
type reg_var = { reg_dest : var_id; source : var_id }
-type ram_var = { ram_dest : var_id;
+type ram_var = { ram_id : int;
addr_size : int; word_size : int;
- read_addr : var_id; write_enable : var_id;
+ write_enable : var_id;
write_addr : var_id; data : var_id }
type dumb_exp =
@@ -29,6 +29,7 @@ type dumb_exp =
| Dconcat of var_id * var_id
| Dslice of int * int * var_id
| Dselect of int * var_id
+ | Dreadram of int * var_id
type dumb_equation = var_id * dumb_exp
@@ -123,28 +124,23 @@ let make_program_dumb p =
| _ -> regs, (n, eq)::eqs)
([],[])
p.p_eqs in
- (* Extract rams *)
+ (* Extract rams, replace arguments by variable id's *)
+ let ram_id = ref 0 in
let rams, eq3 = List.fold_left
(fun (rams, eqs) (n, eq) ->
- match eq with
+ let ram2 = ref None in
+ let eq2 = match eq with
| Eram(asz, wsz, ra, we, wa, d) ->
- {
- ram_dest = var_id n;
+ ram_id := !ram_id + 1;
+ ram2 := Some({
+ ram_id = !ram_id - 1;
addr_size = asz;
word_size = wsz;
- read_addr = arg_id ra;
write_enable = arg_id we;
write_addr = arg_id wa;
data = arg_id d;
- }::rams, eqs
- | _ -> rams, (n, eq)::eqs)
- ([],[])
- eq2 in
-
- (* Replace arguments by variable id's *)
- let eqs = List.map
- (fun (n, eq) ->
- (var_id n, match eq with
+ });
+ Dreadram(!ram_id - 1, arg_id ra)
| Earg(a) -> Dcopy(arg_id a)
| Enot(a) -> Dnot(arg_id a)
| Ebinop(o, a, b) -> Dbinop(o, arg_id a, arg_id b)
@@ -153,16 +149,22 @@ let make_program_dumb p =
| Econcat(a, b) -> Dconcat(arg_id a, arg_id b)
| Eslice(u, v, a) -> Dslice(u, v, arg_id a)
| Eselect(i, a) -> Dselect(i, arg_id a)
- | _ -> failwith "This should not happen."))
- eq3 in
+ | _ -> failwith "This should not happen."
+ in
+ (match !ram2 with | None -> rams | Some k -> k::rams),
+ (var_id n, eq2)::eqs
+ )
+ ([],[])
+ eq2 in
+ (* Replace arguments by variable id's *)
{
d_vars = List.rev (!vars);
d_inputs = List.map var_id p.p_inputs;
d_outputs = List.map var_id p.p_outputs;
d_regs = regs;
- d_rams = rams;
- d_eqs = eqs;
+ d_rams = List.rev rams;
+ d_eqs = eq3;
}
@@ -177,6 +179,7 @@ let c_rom = 4
let c_concat = 5
let c_slice = 6
let c_select = 7
+let c_readram = 8
let binop_id = function
| Or -> 0
@@ -206,8 +209,8 @@ let print_dumb_program oc p =
fprintf ff "%d %d\n" r.reg_dest r.source) p.d_regs;
(* print ram list *)
fprintf ff "%d\n" (List.length p.d_rams);
- List.iter (fun r -> fprintf ff "%d %d %d %d %d %d %d\n"
- r.ram_dest r.addr_size r.word_size r.read_addr r.write_enable
+ List.iter (fun r -> fprintf ff "%d %d %d %d %d\n"
+ r.addr_size r.word_size r.write_enable
r.write_addr r.data) p.d_rams;
(* print equation list *)
fprintf ff "%d\n" (List.length p.d_eqs);
@@ -220,7 +223,8 @@ let print_dumb_program oc p =
| Drom(u, v, a) -> fprintf ff "%d %d %d %d\n" c_rom u v a
| Dconcat(a, b) -> fprintf ff "%d %d %d\n" c_concat a b
| Dslice(u, v, a) -> fprintf ff "%d %d %d %d\n" c_slice u v a
- | Dselect(i, a) -> fprintf ff "%d %d %d\n" c_select i a)
+ | Dselect(i, a) -> fprintf ff "%d %d %d\n" c_select i a
+ | Dreadram(i, k) -> fprintf ff "%d %d %d\n" c_readram i k)
p.d_eqs;
(*flush*)
fprintf ff "@."
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-21 16:04:01 +0000